An embodiment relates generally to a nonvolatile memory device and, more particularly, to the gate patterns of a nonvolatile memory device and a method of forming the same.
Active research is being carried out on nonvolatile memory devices, particularly NAND flash memory devices that can be easily highly integrated. A memory cell of the NAND flash memory device includes a gate in which a floating gate, a dielectric layer, and a control gate are stacked. The stacked gate is formed over a semiconductor substrate with a tunnel insulating layer interposed therebetween. In such a NAND flash memory device, program and erase operations are performed by controlling the threshold voltage of the memory cell in such a way as to inject or discharge electrons into or from the floating gate using the Fowler-Nordheim tunneling method.
Voltage (Vf) induced in the floating gate is determined by the coupling ratio and voltage (Vc) applied to the control gate as shown in Equation below. The coupling ratio is a ratio of capacitance (Cip) of the dielectric layer to the sum of capacitance (Ctn) of the tunnel insulating layer and the capacitance (Cip) of the dielectric layer.
  Vf  =            Cip              Cip        +        Ctn              ⁢    Vc  
Thus, if the equivalent oxide thickness (EOT) (i.e., the thickness of the tunnel insulating layer or the dielectric layer) is uniform, the threshold voltages of memory cells can be uniformly controlled. In a process of forming the memory cell gate, the thickness of the tunnel insulating layer or the dielectric layer of the memory cell may vary.
The memory cell gate of a conventional NAND flash memory device is described below in more detail with reference to FIGS. 1 and 2.
Referring to FIG. 1, the memory cell gate of the NAND flash memory device includes a first conductive layer 5 for a floating gate, a dielectric layer 11, and a second conductive layer 13 for a control gate stacked over a tunnel insulating layer 3.
In order to form the memory cell gate, the tunnel insulating layer 3 and the first conductive layer 5 are first stacked over a semiconductor substrate 1. The first conductive layer 5 and the tunnel insulating layer 3 formed over isolation regions B are removed, and the isolation regions B of the semiconductor substrate 1 are etched to form trenches. Through formation of the trenches, active regions A of the semiconductor substrate 1 are defined, and the tunnel insulating layer 3 and the first conductive layer 5 remain over the active regions A.
Next, in order to remove defects generated on surfaces of the trenches and the first conductive layer 5, an oxidation process is performed to form a sidewall oxide layer 7. Referring to FIG. 2, the oxidation process for removing defects generated on the surfaces of the trenches and the first conductive layer 5 is performed using H2O or O2. Here, H2O or O2 molecules are diffused from the side of the tunnel insulating layer 3 to the interface of the tunnel insulating layer 3 and the semiconductor substrate 1, thus oxidizing an upper edge X1 of the active region of the semiconductor substrate 1. Furthermore, the H2O or O2 molecules are diffused from the side of the tunnel insulating layer 3 to the interface of the tunnel insulating layer 3 and the first conductive layer 5, thus oxidizing a lower edge X2 of the first conductive layer 5. Consequently, the thickness of the edges of the tunnel insulating layer 3 is increased.
After the sidewall oxide layer 7 is formed, an isolation layer 9 comprising insulating material is formed within each of the trenches. In order to densify the film of the insulating material constituting the isolation layer 9, a thermal process, such as annealing, can be performed. The thermal process can increase the thickness of the edges of the tunnel insulating layer 3.
Next, the dielectric layer 11 and the second conductive layer 13 are deposited over the semiconductor substrate 1, and the second conductive layer 13, the dielectric layer 11, and the first conductive layer 5 are patterned. In order to remove defects generated on surfaces of the first and second conductive layers 5 and 13, another oxidation process can be performed. The oxidation process may increase the thickness of the edges of the dielectric layer 11.
As described above, a change in the thickness of the tunnel insulating layer 3 or the dielectric layer 11 may be caused, which may change the coupling ratio between the memory cells, resulting in poor distribution of the threshold voltages of the memory cells.